Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network. Moreover, the first capacitor network comprises a second set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the second set is connected to the second node and the second terminal of each capacitor in the first set is connected to the switch network. The SAR ADC further comprises a second capacitor network configured to control a gain of the SAR ADC.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.

An object of the present disclosure is to prevent an output level of an analog signal from exceeding a predetermined upper limit value, in a module that adjusts a level of the analog signal. According to the present disclosure, there is provided a signal generation apparatus including an RF base module (12) that converts a digital base band signal for testing into an intermediate frequency (IF) signal and outputs the IF signal, and a control unit (18), in which the RF base module is connected to an RF converter (20) which outputs an analog RF signal obtained by frequency-converting the IF signal, and the control unit clips the IF signal output from the RF base module based on an output level of the analog RF signal output from the RF converter.

A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

Methods and systems for an asynchronous successive approximation register analog-to-digital converter with word completion may include a successive approximation register (SAR) analog-to-digital converter (ADC) including a switched capacitor digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector. The SAR ADC may sample a received analog electrical signal using the DAC, and convert the electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator. If the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit. The converting may be initiated using a conversion enable clock pulse generated in the first SAR ADC. The metastability flag may be generated when a conversion enable pulse overlaps with a sampling clock pulse.

A phase-locked loop circuit included in a computer system includes time-to-digital converter and digital-to-time converter circuits. During a mode to test the time-to-digital converter circuit, the digital-to-time converter circuit is coupled to the time-to-digital converter circuit in a loop-back fashion. A control circuit supplies stimulus codes to the digital-time-converter circuit, which generates multiple delayed versions of a reference clock signal using the stimulus codes. The time-to-digital converter circuit, in turn, generates capture codes based on the delay between the reference clock signal and the delayed versions of the reference clock signal. The control circuit compares the capture codes to the stimulus codes to determine a linearity of a response of the time-to-digital converter circuit.

A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.