Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.

The device transforms an analog input signal with N components x(0), x(1) . . . x(N−1) into an output signal with N components X(0), X(1) . . . X(N−1) functions of said components x(0), x(1) . . . x(N−1), said device comprising basic addition and/or subtraction cells linked in a butterfly-type architecture to perform said functions, each basic cell comprising an operator performing a conditional division by two of the result of the addition operation or subtraction operation performed, the condition being the saturation of said operator.

An audio codec integrated circuit (IC), comprising: an audio input interface; an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, the routing circuitry configurable by at least one select pin to adjust the order of routing of the plurality of audio input signals to the data converters or the order of routing of the plurality of audio output signals from the data converters.

The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

A fingerprint signal processing system for a fingerprint sensor includes a calibration control circuit, a register circuit, a decode circuit and a normalization circuit. The calibration control circuit is configured to receive a background calibration control signal and an image signal from the fingerprint sensor, and convert the image signal into a plurality of digital signals according to a plurality of offsets. When the background calibration control signal is at a high level, the calibration control circuit is configured to read a plurality of calibration parameters from the register circuit.

Disclosed are an image sensor, an operating method thereof, and an electronic device including the image sensor. The image sensor includes a pixel array including a plurality of pixels, a first selection/read-out circuit, a second selection/read-out circuit, and a controller provided to select a pixel of the pixel array and control the first and second selection/read-out circuits to read out information of the selected pixel. The first selection/read-out circuit provides a signal for selecting a pixel of the pixel array in a first direction, reads out a plurality of pixel signals received from the pixel array in a direction corresponding to the first direction, and the second selection/read-out circuit provides a signal for selecting a pixel of the pixel array in a second direction, and reads out a plurality of pixel signals received from the pixel array in a direction corresponding to the second direction.

Provided is a low voltage and compact digital control regulator that achieves enhanced stability and reduced variations in ripple voltage and droop characteristics. The digital control regulator includes a first A/D converter configured to generate a first digital signal according to a differential voltage between an output voltage and a first reference voltage, an output stage circuit configured to generate the output voltage, a replica circuit having the same circuit configuration as the output stage circuit and configured to output a replica voltage related to the output voltage, a second A/D converter configured to generate a second digital signal according to a differential voltage between the replica voltage and a second reference voltage, and a control circuit configured to generate a control signal for controlling a gain of the output stage circuit, according to the first digital signal and the second digital signal.

Analog-to-information converter and method for performing analog-to-information conversion samples and down-converts N samples of an input multi-band signal using M analog sampling filters or samplers, where N is less than M. The N samples of the input multi-band signal are digitized to produce N digital samples of the input multi-band signal, which are multiplexed into M digital samples of the input multi-band signal. The M digital samples are up-converted and filtered at M digital reconstruction filters to produce a digital multi-band signal, which is processed at a processing unit to obtain information contained in the digital multi-band signal.

In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.