Methods and systems for performing analog-to-digital conversion are proposed. In one example, An analog-to-digital converter (ADC) comprising a quantizer, the quantizer having a first quantization resolution for a first quantization operation subrange and a second quantization resolution for a second quantization operation subrange. At least one of the first quantization resolution or the first quantization operation subrange is programmable. At least one of the second quantization resolution or the second quantization operation subrange is programmable. The quantizer is configured to: receive an input voltage; and based on whether the input voltage belongs to the first quantization operation subrange or to the second quantization operation subrange, quantize the input voltage at the first quantization resolution or at the second quantization resolution to generate a digital output.

Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer 2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer 2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

A data translation system (100) for performing a non-linear data translation on a digitized AC signal is provided. The non-linear data translation system (100) includes an input for receiving the digitized AC signal, an output for outputting a non-linearly translated signal, and a processing system (104) coupled to the input and to the output. The processing system (104) is configured to receive the digitized AC signal, non-linearly translate the digitized AC signal using a predetermined transfer function to create the non-linearly translated signal, and transfer the non-linearly translated signal to the output.

Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer?2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a front-end configured to receive an analog input signal, wherein the front-end comprises an analog-to-digital converter configured to convert the analog input signal into a digital signal; a digital signal processor configured to receive and process said digital signal; wherein the front-end further comprises a compressor operatively coupled to an input of the analog-to-digital converter, wherein said compressor is configured to apply a compressor function to the analog input signal before said analog input signal is provided to the analog-to-digital converter. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived.