The present disclosure concerns an electronic device connected to an antenna. The electronic device delivers a first amplitude-modulated analog signal of a signal captured by the antenna, the capture signal associated with an electromagnetic field exhibiting intervals at a minimum level. The electronic device includes a first circuit, a second circuit, and a third circuit. The first circuit delivers a second analog signal by rectification and filters the first analog signal. The second circuit delivers a first binary signal based on the demodulation of the second analog signal. The third circuit couples the antenna to a resistor during each pause. The resistance value of the resistor depends on the maximum amplitude of the electromagnetic field before the pause.

A method for demodulating an RF signal to polar in-phase and quadrature (IQ) components that includes converting an RF signal with an analog-to-digital converter and calculating the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using a digital processor. The analog-to-digital converter uses a sampling rate, where, when the sampling rate used has sampling rates other than 3 times an RF carrier frequency of the RF signal, a digital logic circuit splines data to the sampling rate of 3 times the RF carrier frequency of the RF signal. The digital processor calculates the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using addition, subtraction, multiplication, division, and absolute value.

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

A photoelectric conversion apparatus includes a pixel which includes a photoelectric conversion element; a signal line connected with the pixel; a voltage-current conversion unit configured to convert a voltage signal of the signal line into current; and a conversion unit that includes an oversampling type analog-to-digital conversion circuit that converts the current outputted from the voltage-current conversion unit into digital signals. The voltage-current conversion unit converts the voltage signal of the signal line into the current without sampling and holding and outputs the converted current to the conversion unit.

An ultrasound circuit comprising a trans-impedance amplifier (TIA) with built-in time gain compensation functionality is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA is, in some cases, followed by further analog and digital processing circuitry.

Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.