The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

A circuit having a capacitance driver circuit can allow for reduction of thermal noise to an application circuit. An output of the capacitance driver circuit can drive a capacitor for use by the application circuit coupled to the capacitor at the output of the capacitance driver circuit. The capacitance driver circuit can be structured to operate over a bandwidth of interest. With an input signal, received at the capacitance driver circuit, associated with a target voltage, an output voltage can be provided at the output of the capacitance driver circuit as a bandlimited filtered voltage value of the target voltage, where a root-mean-square voltage deviation of the output voltage from the target voltage, due to thermal noise, is less than a square root of (kT/C). The term k is Boltzmann's constant, T is Kelvin temperature of the capacitance driver circuit, and C is the capacitance of the driven capacitor.

Provided are a scalable analog passive intermodulation (PIM) module, a method of controlling analog PIM, a signal processing circuit, and a sensor device. The scalable analog PIM module includes a first plural number of digital-to-analog converters (DACs), a first plural number of static random access memory (SRAM) calculators connected to the first plural number of DACs, at least one analog-to-digital converter (ADC) connected to the first plural number of SRAM calculators and configured to convert an analog convolution result signal into digital convolution data, and an analog PIM controller configured to output an enable control signal for enabling a second number, which is equal to or less than first plural number, of SRAM calculators among the first plural number of SRAM calculators to the first plural number of SRAM calculators on the basis of the convolution data output from the ADC.

A hookah device (202) which attaches to a hookah (246). The hookah device (202) comprises a plurality of ultrasonic mist generator devices (201) for generating a mist for inhalation by a user. The hookah device (202) comprises a driver device (202) which controls the mist generator devices (201) to maximize the efficiency of mist generation by the mist generator devices (201) and optimize mist output from the hookah device (202).

An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

An embodiment electronic circuit includes an electronic switch comprising a load path, a first protection circuit configured to generate a first protection signal based on a current-time-characteristic of a load current through the load path of the electronic switch, and a drive circuit configured to drive the electronic switch based on the first protection signal. The first protection circuit includes an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current, to sample the ADC input signal once in each of a plurality of successive sampling periods, and to output an ADC output signal that includes a sequence of values such that each of the values represents a respective sample of the ADC input signal. The ADC is configured to pseudo-randomly select a sample time in each sampling period.

An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.