An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.

An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.

An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

An analog-to-digital converter may include an integrator, a gated ring oscillator, a coarse counter, a phase state register, a counter register, and logic circuitry. The gated ring oscillator may output a phase state signal continuously to the phase state register. The phase state signal includes multiple phase nodes, each of which is created by transmitting a signal through a number of delay stages. One of the phase nodes may be provided to the coarse counter. The phase state register and counter register may store the most current corresponding phase state and coarse counter outputs, respectively. A control signal corresponding to an analog image input signal may control the output of stored phase states and stored coarse counter outputs to the logic circuitry. The logic circuitry may generate a digital version of the analog image input signal based on the outputs of the phase state and counter registers.

The disclosure provides a data acquisition device. The data acquisition device includes a sensor that detects a physical quantity as analog data; a digital storage circuit that stores the physical quantity as digital data; a difference circuit that calculates a difference between a previous value of the physical quantity stored in the digital storage circuit and a current value of the physical quantity detected as analog data; and a comparison circuit that compares the difference with a predetermined threshold value; and a control unit. The control unit stores a value calculated by adding or subtracting a predetermined change amount to a previous value of the physical quantity stored in the digital storage circuit as the current value, when the difference exceeds or falls below the threshold value. Since the physical quantity is updated without executing A/D conversion, a decrease in the sampling frequency is suppressed.