A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

The inventive concept relates to a method and system for cost-effectively predicting the dynamic nonlinearities of on-chip segmented digital-to-analog converter (DAC) and analog-to-digital-converter (ADC), by looping a DAC to an ADC, using a programmable-gain-amplifier (PGA) and an external load board. The method may include a first loopback step of supplying an output signal from a coarse DAC, to which a sinusoidal signal is supplied, to a coarse ADC and a fine ADC through an external load board, a second loopback step of supplying an output signal from a fine DAC, to which a sinusoidal signal is supplied, to the fine ADC and the coarse ADC through the load board, and a step of predicting dynamic nonlinearity of each of a DAC and an ADC by processing equations exhibiting dynamic nonlinearity of a sub-DAC and a sub-ADC, which are obtained in the first loopback step and the second loopback step.

A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating; the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

An image sensor may include an array of image sensor pixels that are read out using analog-to-digital converters (ADCs). The ADC may be shot-noise-matched to reduce the number of decision cycles required. A ramp with limited resolution spanning only a small portion of the full scale voltage range may be used. For small analog input voltages, this limited ramp range is sufficient. For large analog input voltages, less resolution is needed due to the increasing shot noise in the photo signal. The larger input voltages may be successively divided by a selected attenuation factor until the analog input signal is within the range of the reduced ramp. The ADC keeps track of the number of divisions being performed to determine an exponent value for a floating-point output value and then convert the residual signal with the smaller ramp to determine a mantissa value for the floating-point output value.