One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a receiver device may identify an analog to digital converter (ADC) clipping rate for one or more measurement windows. The receiver device may modify, based at least in part on a determination that the ADC clipping rate does not satisfy a threshold, a low noise amplifier (LNA) gain value to be used by the receiver device. The receiver device may receive a signal using the modified LNA gain value. Numerous other aspects are provided.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a receiver device may identify an analog to digital converter (ADC) clipping rate for one or more measurement windows. The receiver device may modify, based at least in part on a determination that the ADC clipping rate does not satisfy a threshold, a low noise amplifier (LNA) gain value to be used by the receiver device. The receiver device may receive a signal using the modified LNA gain value. Numerous other aspects are provided.

The dynamic range and power efficiency of a voice-activated system may be improved by dynamically adjusting the configuration of the voice-activated system's input path. In one embodiment, a first portion of audio may be received through an input path of the voice-activated system having a first configuration. A characteristic of the first portion of audio may be determined and the input path may be adjusted to a second configuration based on the determined characteristic. A second portion of audio may then be received through the input path having the second configuration, and speech analysis may be performed on the second portion of audio.

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal.

Analog-to-digital conversion circuitry for generating a digital output signal is disclosed comprising a sample-and-hold circuit comprising an adjustable sample capacitor for coupling to an analog input signal during a sample phase, and an analog-to-digital converter (ADC) coupled to an output of the sample-and-hold circuit during a hold phase. In order to compensate in real-time for an increase in an amplitude of the input signal, a capacitance of the sample capacitor is decreased by an attenuation factor, and an output of the ADC is multiplied by an inverse of the attenuation factor to generate the digital output signal.

Analog-to-digital conversion circuitry for generating a digital output signal is disclosed comprising a sample-and-hold circuit comprising an adjustable sample capacitor for coupling to an analog input signal during a sample phase, and an analog-to-digital converter (ADC) coupled to an output of the sample-and-hold circuit during a hold phase. In order to compensate in real-time for an increase in an amplitude of the input signal, a capacitance of the sample capacitor is decreased by an attenuation factor, and an output of the ADC is multiplied by an inverse of the attenuation factor to generate the digital output signal.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

Techniques to adjust a gain of an analog-to-digital converter circuit (ADC) and/or an ADC full scale from one sample to the next of an analog input signal to compensate for the signal loss over distance, which can increase an effective dynamic range of the system. The benefit of compensating for the signal loss due to distance is that a data interface between the ADC of the receiver of the LIDAR system and a signal processor no longer needs to support the dynamic range from the range specification.