A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

Exemplary apparatus can be provided which can include a laser arrangement that is configured to provide a laser radiation, and including an optical cavity. The optical cavity can include a dispersive optical waveguide first arrangement having first and second sides, and which is configured to (i) receive at least one first electro-magnetic radiation at the first side so as to provide at least one second electro-magnetic radiation, and (ii) to receive at least one third electro-magnetic radiation at the second side so as to provide at least one fourth electro-magnetic radiation. The first and second sides are different from one another, and the second and third radiations are related to one another. The optical cavity can also include an active optical modulator second arrangement which can be configured to receive and modulate the fourth radiation so as to provide the first electro-magnetic radiation to the first arrangement. The laser radiation can be associated with at least one of the first, second, third or fourth radiations.

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

A wireless signal digital conversion device according to an embodiment of the present disclosure comprises: a plurality of RF signal processing units for receiving wireless signals, and adjusting the voltage levels of the wireless signals on the basis of automatic gain values; a plurality of unit ADCs for receiving in-phase signals and quadrature phase signals of the RF signal processing units, and performing analog-to-digital conversion on the basis of different differential reference voltages; an encoder unit for generating binary data having less bits than binary data outputted from the unit ADCs on the basis of the binary data outputted from the unit ADCs; and an automatic gain control unit for generating automatic gain values on the basis of the output of a spatial ADC. A terminal of the present disclosure can be linked to an artificial intelligence module, a drone (unmanned aerial vehicle (UAV)), a robot, an augmented reality (AR) device, a virtual reality (VR) device, a device related to 6G services, and the like.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

An arithmetic circuit includes an auto-zero amplification circuit that compensates an offset of an entered differential signal, and a comparator circuit that converts an output signal from the auto-zero amplification circuit to a digital signal. The auto-zero amplification circuit and comparator circuit are provided in the same package.

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2.sup.(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2.sup.(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.