A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

Exemplary apparatus can be provided which can include a laser arrangement that is configured to provide a laser radiation, and including an optical cavity. The optical cavity can include a dispersive optical waveguide first arrangement having first and second sides, and which is configured to (i) receive at least one first electro-magnetic radiation at the first side so as to provide at least one second electro-magnetic radiation, and (ii) to receive at least one third electro-magnetic radiation at the second side so as to provide at least one fourth electro-magnetic radiation. The first and second sides are different from one another, and the second and third radiations are related to one another. The optical cavity can also include an active optical modulator second arrangement which can be configured to receive and modulate the fourth radiation so as to provide the first electro-magnetic radiation to the first arrangement. The laser radiation can be associated with at least one of the first, second, third or fourth radiations.

Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

An image forming includes a dither processing unit that applies a dither matrix to an image; an exposure unit that exposes a photosensitive drum to form an electrostatic latent image based on the image to which the dither matrix has been applied; a development unit that develops, using a developing material on a developing roller, the formed electrostatic latent image; and a control unit that, based on a print setting change instruction by a user, increases a circumferential speed of the developing roller relative to the circumferential speed of the photosensitive drum and decreases a screen ruling of the dither matrix to be applied by the dither processing unit.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

Provided are an apparatus and a method for measuring a frequency of a broadband signal by using low-speed ADCs having sub-Nyquist sampling rates. A plurality of channels each including a low-speed ADC having a sub-Nyquist sampling rate (e.g. sampling frequency from several MHz to hundreds of MHz) are provided, and the frequency of an input signal corresponding to a combination of frequencies calculated through the respective channels is estimated. Therefore, as the number of channels increases, the range of measurable frequencies may be extended.

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.