According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.

In an embodiment, a method includes: resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the respective count values, receiving a plurality of digital addresses from a time-to-digital converter (TDC); during an integration period, for each received digital address, selecting one analog counter based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, where each analog counter has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

In an embodiment, a method includes: resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the respective count values, receiving a plurality of digital addresses from a time-to-digital converter (TDC); during an integration period, for each received digital address, selecting one analog counter based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, where each analog counter has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.

A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.

Analog signal measurement and related circuitry, systems, and methods are disclosed. Circuitry includes timing circuitry configured to assert a first enable signal at a first time and a second enable signal at a second time. The circuitry also includes an operational amplifier circuit configured to enable responsive to the assertion of the first enable signal. The operational amplifier circuit is configured to receive an analog input signal and, if enabled, generate an amplified analog input signal responsive to the analog input signal. The circuitry further includes signal analyzing circuitry configured to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.

Analog signal measurement and related circuitry, systems, and methods are disclosed. Circuitry includes timing circuitry configured to assert a first enable signal at a first time and a second enable signal at a second time. The circuitry also includes an operational amplifier circuit configured to enable responsive to the assertion of the first enable signal. The operational amplifier circuit is configured to receive an analog input signal and, if enabled, generate an amplified analog input signal responsive to the analog input signal. The circuitry further includes signal analyzing circuitry configured to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.

A device can include analog circuits formed with a substrate, including a comparator, analog switches, and a balance current circuit. A sensor current and balance current can be applied at an input of the comparator. The sensor current, balance current or both can be modulated with a switch control signal. Digital circuits can include switch control logic that generates the switch control signal in response to an output of the comparator and a modulation clock signal. Digital signal processing circuits can generate a multi-bit digital value from a bit stream output by the comparator circuit. The multi-bit digital value can be an analog-to-digital conversion of the sensor current. Corresponding methods and systems are also disclosed.