An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.

A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Demodulation circuitry includes an input terminal configured to be coupled to an analog-to-digital converter (ADC) and configured to receive a plurality of ADC outputs. The plurality of ADC outputs are generated based on resolver outputs. The demodulation circuitry also includes a rectifier configured to rectify the plurality of ADC outputs. Rectifying the plurality of ADC outputs preserves a phase of the plurality of ADC outputs. The demodulation circuitry includes amplitude determination circuitry configured to determine, based on the rectified plurality of ADC outputs, demodulated amplitude values corresponding to the resolver outputs. The demodulation circuitry further includes angle computation circuitry configured to generate position outputs based on the demodulated amplitude values.

A vehicle includes a multi-core processor having first, second, and cores and having first and second analog-to-digital converters (ADC) associated with the first and second cores, respectively. The first and second ADC are configured to convert analog phase currents to first and second digital phase current values, respectively. The multi-core processor is configured to generate first and second rotor-angle data from digital signals representing a position of the electric machine. The processor is programmed to, via the first core, estimate a first output torque of the electric machine based on the first rotor-angle data and the first digital phase current values, via the second core, estimate a second output torque based on the second rotor-angle data and the second digital phase current values, and, via the third core, command de-activation of the electric machine in response to a difference between the first and second output torques exceeding a threshold.

According to one aspect of the invention, a method for making relatively high resolution measurements using relatively low resolution devices includes the steps of: deriving a first anticipated measurement value; using the first anticipated measurement value as an initial feed-forward signal; comparing the initial feed forward signal to a received signal from a sensor, thereby generating a compared signal; scaling the compared signal to full scale of an analog-to-digital converter, thereby generating a scaled signal; delivering the scaled signal in binary form for computation; and iteratively performing the comparing step until the compared signal is below a predetermined threshold value.

Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

The voltage variation detection circuit includes: a threshold voltage generation circuit arranged to generate a threshold voltage; a comparator arranged to compare a variation detection-target voltage and the threshold voltage to each other; and a controller arranged to control the threshold voltage generation circuit based on output of the comparator. Repeated are operations of: decreasing the threshold voltage stepwise; when the variation detection-target voltage has come to the threshold voltage or more, first increasing the threshold voltage by specified steps and then again decreasing the threshold voltage stepwise; and when the variation detection-target voltage has come to the threshold voltage or more, increasing the threshold voltage by specified steps. The controller detects a variation of the variation detection-target voltage based on control results at time points when the variation detection-target voltage comes to the threshold voltage or more.

A method for cartesian (IQ) to polar phase conversion includes: converting a first input value into a first absolute value, and a second input value into a second absolute value; converting the first absolute value into a first logarithmic value by calculating a scaled logarithmic value of the first absolute value, and the second absolute value into a second logarithmic value by calculating a scaled logarithmic value of the second absolute value; subtracting the first logarithmic value from the second logarithmic value, to provide a subtract value; and selecting a phase value from a plurality of phase values stored in a storage unit. Each of the plurality of phase values corresponds to a respective index value, and the phase value is selected taking the subtract value as the index value.

An apparatus includes a coarse resolver configured to output coarse position signals indicative of a coarse position of a drive shaft of a motor. The apparatus also includes a fine resolver configured to output fine position signals indicative of a fine position of the drive shaft of the motor. The apparatus further includes a control circuit. The control circuit is configured to receive the coarse position signals from the coarse resolver and the fine position signals from the fine resolver and generate an initial position output, based on the coarse position signals, that indicates an initial position of the drive shaft. The control circuit is further configured to generate a subsequent position output, based on the fine position signals, that indicates a subsequent position of the drive shaft.

A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.