An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

A method and apparatus for processing a periodic analog signal using a composite ADC including a time interleaved set of sub-ADCs, to produce a replica signal representative of the analog signal, wherein the replica signal is characterized by suppression of additive noise on the periodic analog signal, and correction of sub-ADC-caused distortions. Streams of samples from the respective sub-ADCs are accumulated separately for respective positions in signal periods of the periodic analog signal to provide sub-replicas. Fourier transforms of the replicas are determined for the different sub-ADCs, and those Fourier transforms are averaged to obtain a mean Fourier transform. Frequency responses of the sub-ADCs are corrected by dividing the mean Fourier transform by the respective sub-ADC frequency responses. An averaged replica of the signal period is obtained by determining an inverse Fourier transform of the corrected mean Fourier transform.

An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V.sub.1 and a second voltage V.sub.2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V.sub.1 and the second voltage V.sub.2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V.sub.1, the second voltage V.sub.2 and the zero-crossing time, wherein V.sub.1 is a first negative voltage before the zero-crossing time, and V.sub.2 is a first positive voltage after the zero-crossing time.