In an embodiment a method includes receiving, at an input of a low-voltage section of a gate driver, a PWM control signal with a switching frequency, providing, at an output of a high-voltage section of the gat driver, a gate-driving signal as a function of the PWM control signal to a power stage, wherein the high-voltage section is galvanically isolated from the low-voltage section, receiving, at a feedback input of the high-voltage section, at least one feedback signal indicative of an operation of the power stage, converting, at an ADC module of the high-voltage section, the feedback signal into a digital data stream, providing, to the ADC module, a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal and sending, via an isolation communication channel between the low-voltage section and the high-voltage section, the digital data stream to the low-voltage section.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

A drive circuit, comprising: a target waveform conversion part, configured to convert target waveform information into a current or voltage signal, and output the converted current or voltage signal to a first sampling circuit and a second sampling circuit; a computational module, the computational module outputting an action command on the basis of the output results of the first sampling circuit and the second sampling circuit; and a TDC module for outputting time parameters of a counting interval on the basis of the action command outputted by the computational module. By means of the present circuit, time information of a predetermined interval can be automatically acquired, for example time information of a rising edge or a falling edge, and can then be used to calibrate emission or calibrate the final ranging result of a time-of-flight ranging solution, such that the emitted light waveform of an emission source is more accurate or the ranging result is more accurate.

A drive circuit, comprising: a target waveform conversion part, configured to convert target waveform information into a current or voltage signal, and output the converted current or voltage signal to a first sampling circuit and a second sampling circuit; a computational module, the computational module outputting an action command on the basis of the output results of the first sampling circuit and the second sampling circuit; and a TDC module for outputting time parameters of a counting interval on the basis of the action command outputted by the computational module. By means of the present circuit, time information of a predetermined interval can be automatically acquired, for example time information of a rising edge or a falling edge, and can then be used to calibrate emission or calibrate the final ranging result of a time-of-flight ranging solution, such that the emitted light waveform of an emission source is more accurate or the ranging result is more accurate.

An analog-to-digital converter (1) includes an S/H circuit (10) that samples and holds an analog input signal in synchronization with a first sampling clock signal (CLK1), a filter circuit (20) that smooths an output signal of the S/H circuit (10), and an ADC circuit (30) that samples an output signal of the filter circuit (20) in synchronization with a second sampling clock signal (CLK2) different from the first sampling clock signal (CLK1), and outputs a digital signal corresponding to an amplitude of the output signal that is sampled.

An analog-to-digital converter (1) includes an S/H circuit (10) that samples and holds an analog input signal in synchronization with a first sampling clock signal (CLK1), a filter circuit (20) that smooths an output signal of the S/H circuit (10), and an ADC circuit (30) that samples an output signal of the filter circuit (20) in synchronization with a second sampling clock signal (CLK2) different from the first sampling clock signal (CLK1), and outputs a digital signal corresponding to an amplitude of the output signal that is sampled.

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.