An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

A method for light-to-frequency conversion comprises generating a photocurrent by means of a photodiode and converting the photocurrent into a digital comparator output signal in a charge balancing operation depending on a first clock signal. From the digital comparator output signal an asynchronous count is determined and comprises an integer number of counts depending on the first clock signal. From the digital comparator output signal a fractional time count is determined and depends on a second clock signal. Finally, from the asynchronous count and from the fractional time count a digital output signal is calculated which is indicative of the photocurrent generated by the photodiode. The method may be carried out by an exemplary light-to-frequency converter equipped with a photodiode.

A method for light-to-frequency conversion comprises generating a photocurrent by means of a photodiode and converting the photocurrent into a digital comparator output signal in a charge balancing operation depending on a first clock signal. From the digital comparator output signal an asynchronous count is determined and comprises an integer number of counts depending on the first clock signal. From the digital comparator output signal a fractional time count is determined and depends on a second clock signal. Finally, from the asynchronous count and from the fractional time count a digital output signal is calculated which is indicative of the photocurrent generated by the photodiode. The method may be carried out by an exemplary light-to-frequency converter equipped with a photodiode.

A device is provided comprising a first oscillator based analog-to-digital converter configured to receive an analog input signal and output a first digital signal and a second oscillator based analog-to-digital converter configured to receive an analog reference signal and output a second digital signal. The device further comprises output logic configured to generate a digital output signal based on the first digital signal and the second digital signal.

A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit (200) receives an analogue input signal (S.sub.IN) and outputs a digital output signal (S.sub.OUT). The circuit has a sampling capacitor (101), a controlled oscillator (104) and a counter (106) for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor (102) is coupled to an input node for the input signal, e.g. via switch (102a). In the read-out phase, the sampling capacitor is coupled to the controlled oscillator (104), e.g. via switch (102b), such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.