A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.

A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.

A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.

A modulo-based ADC implementation is provided and involves converting an input analog signal into phases of other M periodic analog reference signals based on one or more transfer functions, wherein M2. The phase of each of the M reference signals comprises a folded signal corresponding to the input analog signal that is amplitude-folded to fall within a required amplitude range. This signal-to-phase conversion allows a modulo operation to be implemented over the input analog signal. Further, the M reference signals are used to obtain M discrete-time digital signals which, in turn, are used to obtain a digital representation of the input analog signal.

A modulo-based ADC implementation is provided and involves converting an input analog signal into phases of other M periodic analog reference signals based on one or more transfer functions, wherein M2. The phase of each of the M reference signals comprises a folded signal corresponding to the input analog signal that is amplitude-folded to fall within a required amplitude range. This signal-to-phase conversion allows a modulo operation to be implemented over the input analog signal. Further, the M reference signals are used to obtain M discrete-time digital signals which, in turn, are used to obtain a digital representation of the input analog signal.

A method for calibrating a phase-modulation converter that includes an amplitude modulator with carrier suppression, an adder, a limiter and a demodulation facility to which a signal output by the limiter is suppliable and demodulated therein, wherein a comparison of the signal output by the limiter with a reference signal occurs in the context of the demodulation, a calibration switch, which is connected upstream of the adder which is actuatable between a control setting in which the adder, is connected via the calibration switch to the input of the phase-modulation converter, and at least one calibration setting in which the is interrupted, where in a calibration setting of the calibration switch, the phase position of the reference signal is changed, preferably dynamically, and a phase position of the reference signal is found at which an output signal of the demodulation facility assumes a calibrated value.