Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. Latches may be used at one or more levels of decoding and may be activated according to a clock signal to recapture the at least partially decoded data signals to maintain/improve the synchronicity of activation of the unit cells. However, the latches may consume additional power during operation. As such, clock tracking techniques such as static clock tracking, dynamic clock tracking, or differential clock tracking may be utilized to generate a clock path activation signal that gates the clock signal and determines which latches to ignore (e.g., leave inactive). In this manner, instead of activating each latch for every digital signal, clock tracking may be implemented to deactivate latches that do not provide useful updates to the decoded digital signal received at the unit cells.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

Described herein are apparatus and methods for low speed characterization of a high-speed signal. A circuit includes a sub-sampling circuit configured to sub-sample a high-speed signal received from a device, a reconstruction loop circuit configured to reconstruct a low-speed signal from the sub-sampled high-speed signal, a low pass filter configured to filter the reconstructed low-speed signal, a discrete time low pass filter configured to mitigate skew rate requirements of the filtered low-speed signal for a digitization circuit, a continuous time low pass filter configured to smooth the skew rate mitigated low-speed signal and the digitization circuit is configured to generate a digital representation of the smoothed low-speed signal for characterization by a characterization device, and shape a noise associated with the smoothed low-speed signal outside a frequency range of interest of the smoothed low-speed signal.

Certain aspects of the present disclosure are directed to a digital-to-analog converter (DAC) system. The DAC system generally includes a first current-steering DAC having a positive output, a negative output, and a bypass output; a common-mode (CM) path coupled between the positive and negative outputs; and a CM current compensation path coupled to the CM path.

Certain aspects of the present disclosure are directed to a digital-to-analog converter (DAC) system. The DAC system generally includes a first current-steering DAC having a positive output, a negative output, and a bypass output; a common-mode (CM) path coupled between the positive and negative outputs; and a CM current compensation path coupled to the CM path.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.