A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input of the DAC to transform the first and second upsampled digital signals into an analog pulse sequence signal for controlling the quantum device.

The disclosure provides a data acquisition device. The data acquisition device includes a sensor that detects a physical quantity as analog data; a digital storage circuit that stores the physical quantity as digital data; a difference circuit that calculates a difference between a previous value of the physical quantity stored in the digital storage circuit and a current value of the physical quantity detected as analog data; and a comparison circuit that compares the difference with a predetermined threshold value; and a control unit. The control unit stores a value calculated by adding or subtracting a predetermined change amount to a previous value of the physical quantity stored in the digital storage circuit as the current value, when the difference exceeds or falls below the threshold value. Since the physical quantity is updated without executing A/D conversion, a decrease in the sampling frequency is suppressed.

An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.

Radio transmitters providing an analog signal with both radio frequency (RF) and baseband frequency information are disclosed herein. In certain embodiments, a transmitter for an RF communication system includes a radio frequency digital-to-analog converter (RFDAC) that outputs the analog signal with two bands of content. In particular, the analog signal includes a first band on content at RF frequency and representing the RF signal for transmission, and a second band of content at baseband frequency and representing baseband information such as the envelope of the RF signal.

Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

A digital-to-analog converter and a digital-to-analog conversion method thereof are provided. The digital-to-analog conversion method includes: converting a digital data signal into an analog data signal in a first cycle according to a clock signal, resetting the analog data signal in a second cycle according to the clock signal and a reset signal corresponding to a first reset level, and compensating for a voltage level of the reset analog data signal in the second cycle according to a second reset level, so that the voltage level of the reset analog data signal is the second reset level. The second reset level is higher or lower than the first reset level.

Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

A multi-channel digital to analog converter, DAC, comprising: a DAC configured to provide an analog signal comprising a plurality of time division multiplexed sub-signals, each provided for one of a plurality of output channels; wherein each of the output channels include: a sampling capacitor; a selector switch configured to couple the sampling capacitor of the respective output channel to the output terminal of the DAC such that the sampling capacitor samples the analog signal over a plurality of discrete sampling periods; a comparator configured to provide a comparator output signal, wherein the sampling capacitor is coupled to an input terminal of the comparator; and an output control gate configured to control whether or not the comparator output signal is output from the respective output channel at a predetermined time later than a first of the respective plurality of discrete sampling periods.