A controlled switch having N inputs and a single output (N≥2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.

A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

An audio codec integrated circuit (IC), comprising: an audio input interface; an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, the routing circuitry configurable by at least one select pin to adjust the order of routing of the plurality of audio input signals to the data converters or the order of routing of the plurality of audio output signals from the data converters.

Consistent with the present disclosure, low pass filters are provided in the electrical paths connecting digital to analog converter (DAC) circuitry to an optical block package (also referred to as a “gold box”). The low pass filter blocks or substantially attenuates high frequency noise components present in an analog signal output from the DAC, thereby reducing errors that might otherwise be present in the transmitted data.

A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.