A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

An analog signal processing circuit comprising: a first promoter operably linked to a nucleic acid sequence encoding a first output molecule, wherein said promoter is responsive to a cooperative input signal comprising at least two cooperative inputs, and wherein expression of said at least two cooperative inputs is tunable.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

A method for differentiator-based compression of digital data includes (a) using a subtraction module, subtracting a predicted signal from a sample of an original signal to obtain an error signal, (b) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (c) generating the predicted signal using a least means square (LMS)-based filtering method.

A gamma correction digital-to-analog converter (DAC) includes a first DAC circuit, a second DAC circuit and a voltage generator. The first DAC circuit includes a plurality of first transistors and is configured to receive a plurality of first reference gamma voltages and 1 upper bits of k-bit digital data and generate a first gamma voltage based on the 1 upper bits of the k-bit digital data and the first reference gamma voltages. The second DAC circuit includes a plurality of second transistors and is configured to receive a plurality of second reference gamma voltages and m lower bits of the k-bit digital data and generate a second gamma voltage based on the m lower bits of the k-bit digital data and the second reference gamma voltages. The voltage generator is configured to generate a bulk voltage and supply the generated bulk voltage to a bulk terminal of each of the first transistors or supply the generated bulk voltage to a bulk terminal of each of the second transistors to generate a gamma correction analog signal according to the first gamma voltage and the second gamma voltage. A data driver including a gamma correction DAC and a method thereof are also introduced.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

A process and corresponding system for encoding and decoding digital data in analog signals is disclosed. Digital data values are represented by concurrent combinations of distinct audio tones, which combine to create chords. The chords have multiple identifiable parameters that can be modulated to represent the data values. For instance, the modulated chords can include a concurrent combination of distinct tones that each have a different frequency and a different starting time. The frequencies of the tones and the starting times of those tones can be modulated to create unique combinations that represent respective data values. As such, analog audio content of a given chord can be used to represent a particular data value and the analog audio signals can be transmitted between nodes in a communication network in order to communicate that data value.

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.