This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

Methods, devices, and systems for processing information are disclosed. An example device may comprise a metastructure comprising a plurality of physical features configured to transform an analog signal according to a kernel of an integral equation. The device may comprise one or more waveguides coupled to the metastructure and configured to recursively supply a transformed analog output signal of the metastructure to an input of the metastructure to iteratively cause one or more transformed analog signals output from the metastructure to converge to an analog signal representing a solution to the integral equation.

Methods, devices, and systems for processing information are disclosed. An example device may comprise a metastructure comprising a plurality of physical features configured to transform an analog signal according to a kernel of an integral equation. The device may comprise one or more waveguides coupled to the metastructure and configured to recursively supply a transformed analog output signal of the metastructure to an input of the metastructure to iteratively cause one or more transformed analog signals output from the metastructure to converge to an analog signal representing a solution to the integral equation.

SAR-DAC devices and operation methods of SAR-DAC devices are provided. An exemplary SAR-DAC device includes a comparator having a positive input terminal and a negative input terminal; and a DAC core unit including a first capacitor, a second capacitor, and a current-controlled discharging structure. The first capacitor includes a first charging-discharging terminal. The second capacitor includes a second charging-discharging terminal. The current-controlled discharging structure includes current beam circuit units. Each current beam circuit unit includes a first discharging input terminal connected to the first charging-discharging terminal and a second discharging input terminal connected to the second charging-discharging terminal. The current-controlled discharging structure is configured to discharge the first capacitor through the first discharging input terminal by using at least some of the current beam circuit units; and to discharge the second capacitor through the second discharging input terminal using at least some of the current beam circuit units.

SAR-DAC devices and operation methods of SAR-DAC devices are provided. An exemplary SAR-DAC device includes a comparator having a positive input terminal and a negative input terminal; and a DAC core unit including a first capacitor, a second capacitor, and a current-controlled discharging structure. The first capacitor includes a first charging-discharging terminal. The second capacitor includes a second charging-discharging terminal. The current-controlled discharging structure includes current beam circuit units. Each current beam circuit unit includes a first discharging input terminal connected to the first charging-discharging terminal and a second discharging input terminal connected to the second charging-discharging terminal. The current-controlled discharging structure is configured to discharge the first capacitor through the first discharging input terminal by using at least some of the current beam circuit units; and to discharge the second capacitor through the second discharging input terminal using at least some of the current beam circuit units.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.