A method for compensating signal nonlinearities includes generating a local oscillator (LO) signal and performing phase modulation of the LO signal to generate a phase-modulated LO signal. The phase modulation is based on applying at least one digital-to-time converter (DTC) code of a plurality of DTC codes to a rising edge signal portion and a falling edge signal portion associated with the LO signal. Nonlinearities associated with the rising edge signal portion and the falling edge signal portion are determined. The at least one DTC code is adjusted based on the nonlinearities.

A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

The present invention relates to a method for the analogue multiplication and/or calculation of a scalar product, with a circuit assembly, which has a series circuit comprising a first FET and a second FET, or FET array, serving as a current source, a charging device, and a capacitance, which can be precharged by way of the charging device, and can be discharged by way of the series circuit of the first FET and the second FET, or FET array. The capacitance is initially precharged for the multiplication of a first value by a second value. The first value, encoded as the pulse width of a voltage pulse, is applied to the gate of the first FET, and the second value, encoded as the voltage amplitude, is applied to the gate of the second FET. By this means the capacitance is discharged, for the period of time of the voltage pulse, with a discharge current, which is specified by the voltage amplitude applied to the second FET. The result of the multiplication can then be determined from the residual charge or residual voltage of the capacitance. The method operates very energy-efficiently and can advantageously be used for the execution of calculations in neurons of an artificial neural network.

The present invention relates to a method for the analogue multiplication and/or calculation of a scalar product, with a circuit assembly, which has a series circuit comprising a first FET and a second FET, or FET array, serving as a current source, a charging device, and a capacitance, which can be precharged by way of the charging device, and can be discharged by way of the series circuit of the first FET and the second FET, or FET array. The capacitance is initially precharged for the multiplication of a first value by a second value. The first value, encoded as the pulse width of a voltage pulse, is applied to the gate of the first FET, and the second value, encoded as the voltage amplitude, is applied to the gate of the second FET. By this means the capacitance is discharged, for the period of time of the voltage pulse, with a discharge current, which is specified by the voltage amplitude applied to the second FET. The result of the multiplication can then be determined from the residual charge or residual voltage of the capacitance. The method operates very energy-efficiently and can advantageously be used for the execution of calculations in neurons of an artificial neural network.

An extreme index finder and a digital value finding method are provided. The extreme index finder includes a plurality of digital-to-time converters (DTCs) and a first arbiter apparatus. The DTCs respectively receive a plurality of input signals and perform a digital-to-time converting operation on each of the input signals to respectively generate a plurality of time-domain signals. The first arbiter apparatus finds a position of a extreme value in the time-domain signals according to transition speeds of the time-domain signals and compares transition speed of the extreme value with each of the time-domain signals to find an extreme input signal corresponding to the extreme value in the input signals.

An extreme index finder and a digital value finding method are provided. The extreme index finder includes a plurality of digital-to-time converters (DTCs) and a first arbiter apparatus. The DTCs respectively receive a plurality of input signals and perform a digital-to-time converting operation on each of the input signals to respectively generate a plurality of time-domain signals. The first arbiter apparatus finds a position of a extreme value in the time-domain signals according to transition speeds of the time-domain signals and compares transition speed of the extreme value with each of the time-domain signals to find an extreme input signal corresponding to the extreme value in the input signals.

A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.

An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.