Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A digital pixel sensor for correcting and reducing a mismatch between a pixel and an analog digital converter provided. The digital pixel sensor includes a pixel array including a plurality of pixels; and a bank disposed on the pixel array. The bank includes: a plurality of comparators disposed on the plurality of pixels and configured to compare each of a plurality of pixel signals output from the plurality of pixels with a reference signal to output a plurality of comparison result signals; and a counter connected to the plurality of comparators, and configured to receive the plurality of comparison result signals and latch count code based on the plurality of comparison result signals.

Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal.