An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

An image processing apparatus is applied to a display and includes a sampling unit, a comparing unit, a determining unit and an operating unit. The sampling unit is configured to receive a pulse-width modulation (PWM) signal and sample the PWM signal to output a current image. The comparing unit is coupled to the sampling unit and configured to compare the current image with a previous image to generate a comparison result, wherein the previous image is prior to the current image. The determining unit is coupled to the comparing unit and configured to determine whether the current image is the same with the previous image according to the comparison result and a threshold value. If a determination result of the determining unit is YES, the operating unit stops its operation.

Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that allow an improvement in the rate of modulation of PWM signals. Pulse width modulation (PWM) is performed to convert one of a 0 or 1 represented by a bit of a pulse density modulation (PDM) signal into which an audio signal has been PDM-modulated, into a maximum-length pulse of a maximum pulse width of a PWM signal having a period equal to the period of the PDM signal, and convert the other of the 0 or 1 of the PDM signal into a minimum-length pulse of a minimum pulse width of the PWM signal at a position adjacent to the center of the period of the PWM signal. The present technology is applicable, for example, to audio reproduction systems that reproduce audio signals.

This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (P.sub.Width) and to output a PWM signal (S.sub.PWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.

A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.

There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a cycle in which the state information held by the transition-state acquiring section is updated.

There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a cycle in which the state information held by the transition-state acquiring section is updated.

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.