An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a bandpass noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The bandpass noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

A delta-sigma modulator includes a capacitively-coupled amplifier, a first integrator, a second integrator, a quantizer, a first switch, a second switch, and a control circuit. The first switch is connected between an input of the capacitively-coupled amplifier and a sampling capacitor of the capacitively-coupled amplifier to execute a chopping operation. The second switch is connected between an output of the capacitively-coupled amplifier and an input of the first integrator to execute a chopping operation. The control circuit executes modulation through the first switch at the input of the capacitively-coupled amplifier, executes demodulation through the second switch at the output of the capacitively-coupled amplifier, and imports an output signal of the capacitively-coupled amplifier into the first integrator after the demodulation.

A device may include an input terminal configured to receive an analog input signal. A device may include an output terminal configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal. A device may include an error correction system connected to the ADC, the error correction system including a first input terminal configured to receive an Nth powered version of the digital signal x, wherein N is a whole number equal to or greater than two, wherein the error correction system is configured to: use the Nth powered version of the digital signal x to determine a correction value; and modify the digital signal x to generate a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors occurring within the ADC.

In one or more embodiments, a continuous-time delta-sigma modulator (CTDSM) includes one or more integrators including one or more of a feed-forward loop or a feedback loop and including a one or more capacitive feed-ins to enable insertion of a signal at the outputs of the one or more integrators. The coefficients of one or more of the feed-forward loop, the feedback loop, or the capacitive feed-ins may be configured to shape a signal transfer function of the CTDSM. Additionally, the capacitive feed-ins remove signal components from the integrator outputs, reducing noise and reducing the power consumed by the CTDSM. In one or more embodiments, coefficients of the plurality of capacitive feed-ins may be selected to limit peaking in the signal transfer function (STF) of the CTDSM.