A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

A delta-sigma modulator is provided with: a loop filter 30; a quantizer 36 that generates quantized data on the basis of an output from the loop filter 30; an internal path 42 connected to the loop filter 30 or the quantizer 36; and a compensator 38 that provides, to the internal path 42, a compensation signal for compensating for distortion that occurs in a frequency component at a target frequency, the frequency component being among frequency components of a pulse train corresponding to the quantized data.

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

The present disclosure provides systems and methods for identifying failures in an analog to digital (A/D) converter. An intelligent electronic device (IED) may monitor a digital output of one or more A/D converters. The IED may determine a slope value limit associated with the A/D converter. The IED may determine an output slope value of the digital output based on a difference of a converter output value measured at a first time and a converter output value measured at a later time. If the determined output slope value exceeds the slope value limit, the IED may identify a failure of the A/D converter. An IED may determine that concurrent failures in multiple, parallel A/D converters are indicative of a problem upstream from the A/D converters.

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

[Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system. [Solution] A measurement method of the present embodiment is a measurement method for a delta-sigma type of data converter that performs a data conversion between an analog signal and a digital signal. The measurement method comprises: successively measuring and taking in output digital codes outputted via data conversions performed, by a data converter, on the basis of ramp-waveform inputs generated on the basis of input voltage values at predetermined intervals; selecting and pairing, as pair combinations, those ones of the output digital codes which are different from each other and further adjacent to each other in order of magnitude of value; performing, for each combination, a predetermined statistical processing by use of the output digital codes belonging to the combination or by use of the input voltage values corresponding to these output digital codes; and calculating a nonlinear error from the result of the statistical processing.