In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

A DAC error measurement apparatus includes: an ADC and a feedback DAC, where a measurement input of the ADC includes a square wave signal with a constant frequency, a direct-current signal at a constant logical level, and an analog output of the feedback DAC; a measurement selection module, configured to provide a measured digit in a digital output to a separately selected source cell, and provide remaining digits in the digital output to remaining source cells, where the measured digit is a flippable digit, and the remaining digits are non-flipping digits; and a measurement module, configured to measure an amplitude of the digital output based on the digital output. One flipping digit in the digital output is the measured digit, and the remaining digits are the non-flipping digits, such that the measurement selection module may separately select one source cell to receive the measured digit.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.

A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

In accordance with embodiments of the present disclosure, a method may include, in a system comprising a differential filter comprising a plurality of impedance elements, applying a common-mode signal to the differential filter, measuring an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements, and tuning one or more of the plurality of impedance elements to minimize the error.