An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.

A circuitry for an incremental delta-sigma modulator includes at least an incremental delta-sigma modulator and a sample-and-hold element, the sample-and-hold element being arranged in front of the incremental delta-sigma modulator and providing an input voltage for the incremental delta-sigma modulator in the charged state, wherein the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator, wherein a first switch is arranged in front of the capacitor, and a second switch is arranged behind the capacitor, wherein the first switch is open when the second switch is closed so as to provide, at the incremental delta-sigma modulator, an input voltage decreasing in amount, in particular a decaying input voltage, or wherein the second switch is open when the first switch is closed so as to charge the capacitor of the sample-and-hold element. In addition, a method of operating a circuitry for an incremental delta-sigma modulator is proposed.

An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

A system includes an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal, and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value, and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

Disclosed are a system and a battery management integration circuit using an incremental analog-to-digital converter (ADC), which can reduce the consumption of the amount of a bias current. The system includes an incremental ADC configured to perform accumulation on an analog signal during an oversampling period and a bias current generator configured to provide a bias current for the accumulation of the incremental ADC. The bias current generator provides a first amount of the bias current in a first period defined from start timing of oversampling to preset timing during the oversampling period, and provides a second amount of the bias current, smaller than the first amount of the bias current, in a second period subsequent to the first period.

An RF signal generation device includes an RF signal generation unit 102 that pulse-modulates a prescribed signal to generate an output signal in which four or more-level discrete output levels appear and that a lowest level and any other level appear alternately; a code converter 91 that converts the output signal from the RF signal generation unit 102 into an RF signal in which a smaller number of levels than the number of levels in the output signal; a driver unit 203 that converts the RF signal from the code converter 91 into a binary signal comprising plural bits in which bits corresponding to signal levels in the RF signal are significant; and a digital amplifier 303 that outputs a voltage corresponding to levels in the RF signal outputted from the code converter 91, on the basis of an output signal from the driver unit 203.

A sigma-delta analog-to-digital converter (ADC) includes a feed-forward circuit, a finite-impulse-response (FIR) digital-to-analog converter (DAC), and a decimation filter. The feed-forward circuit is configured to receive an analog input signal and a feedback signal and generate a set of digital signals. Each feedback element of the FIR DAC includes a flip-flop and a reset circuit. The reset circuit is configured to receive a corresponding reset signal of a set of reset signals and output a reference output signal when the corresponding reset signal is deactivated. The reset signal of each feedback element is deactivated sequentially after each cycle of a clock signal that is received by the flip-flop associated with a corresponding reset circuit of each feedback element. The feedback signal is generated based on the reference output signal. The decimation filter is configured to generate a digital output signal based on the set of digital signals.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.