A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

A device can include analog circuits formed with a substrate, including a comparator, analog switches, and a balance current circuit. A sensor current and balance current can be applied at an input of the comparator. The sensor current, balance current or both can be modulated with a switch control signal. Digital circuits can include switch control logic that generates the switch control signal in response to an output of the comparator and a modulation clock signal. Digital signal processing circuits can generate a multi-bit digital value from a bit stream output by the comparator circuit. The multi-bit digital value can be an analog-to-digital conversion of the sensor current. Corresponding methods and systems are also disclosed.

Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.

An ANC system includes an AD converter which performs AD conversion on an external noise signal, an ANC signal generator which generates an ANC signal for canceling a noise component arriving at the ears of a user based on an output signal of the AD converter, and a level detector which detects a level of the output signal and causes the ANC signal generator to power down in response to the level. The level detector measures a time for which the level is equal to or less than a predetermined first threshold value, causes the ANC signal generator or a portion of blocks of the AD converter to power down after the measured time exceeds a predetermined value, and causes the ANC signal generator or a portion of blocks of the AD converter to return from the power down when the level exceeds a predetermined second threshold value.

An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

A differential delta-sigma-modulator has an integrator including a pair of single-ended amplifiers. A sample clock is driving a first switchable capacitor configuration and a second switchable capacitor configuration at a predetermined switching cycle. The first switchable capacitor configuration is adapted for sampling respective outputs from the pair of single-ended amplifiers on a pair of output sampling capacitors in the first part of the switching cycle. The second switchable capacitor configuration is adapted for charging a common mode capacitor with the average voltage of the voltage sampled by the pair of output sampling capacitors in the second part of the switching cycle. The voltage across the common mode capacitor represents the common mode voltage for the integrator.

A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a K.sup.th sampling period, a quantization error signal for a K.sup.th period according to an internal signal, a quantization error signal for a (K−1).sup.th period, a filtered quantization error signal for the (K−1).sup.th period and a filtered quantization error signal for a (K−2).sup.th period; an integrating capacitor configured to store the quantization error signal for the K.sup.th period, to weight the internal signal in a (K+1).sup.th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the K.sup.th period in a K.sup.th discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1).sup.th sampling period and a (K+2).sup.th sampling period; and a comparator configured to quantize the quantization error signal for the K.sup.th period.

The present disclosure relates generally to digital microphone and other sensor assemblies including a transduction element and a successive-approximation (SA) quantizer configured to reuse a digital code generated for a prior sample period for a current sample period when a reuse condition is satisfied. The SA quantizer does not regenerate a new digital code for the current sample period when the digital code generated for the prior sample period is used thereby reducing power consumption.