An analog-to-digital conversion circuit includes a convertor configured to perform a first comparison operation for sensing a noise based on a reset signal and to perform a second comparison operation for sensing raw data to output data which is obtained by removing the noise from the raw data, and a ramp voltage generator configured to generate a ramp voltage used for the first comparison operation and the second comparison operation and to output the ramp voltage to the convertor. The ramp voltage generator includes a first current source for supplying a bias current for generating the ramp voltage in response to a first control signal, a second current source for supplying a boost current for generating the ramp voltage in response to a second control signal, and a generation circuit for generating the ramp voltage based on the bias current and the boost current.

An image sensor may include an array of image pixels arranged in rows and columns. The columns of pixels are coupled to corresponding delta sigma modulators. Each group of delta sigma modulators may be coupled to a column memory circuit. The column memory circuit may receive bits serially from each pixel column in the group. Once all bits in a bit stream from each pixel column have been stored into the column memory circuit, the column memory circuit may output one bit stream at a time to a shared filter circuit. The shared filter circuit may process an entire bit stream associated with a given column in one cycle. Sharing the filter circuit among multiple pixel columns can dramatically reduce circuit area for the image sensor.

A method can include in a first phase of a sensing operation, controlling at least a first switch to energize a sensor inductance; in a second phase of the sensing operation that follows the first phase, controlling at least a second switch to couple the sensor inductance to a first modulator capacitance to induce a first fly-back current from the sensor inductance, the first fly-back current generating a first modulator voltage at the first modulator capacitance, and in response to the first modulator voltage, controlling at least a third switch to generate a balance current that flows in an opposite direction to the fly-back current at the first modulator node. The first and second phases can be repeated to generate a first modulator voltage at the first modulator capacitance. the modulator voltage can be converted into a digital value representing the sensor inductance. Related devices and systems are also disclosed.

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

A photoelectric conversion device includes a light receiving circuit configured to convert light into an electrical signal, a first hold circuit configured to hold a data signal which represents the electrical signal, a second hold circuit configured to hold a noise signal read out from the light receiving circuit in a reset state, a first resistive element to which a voltage corresponding to a difference between the data signal held by the first hold circuit and the noise signal held by the second hold circuit is applied, an A/D converter configured to convert an analog current flowing in the first resistive element into digital data, a second resistive element, and a temperature detection circuit configured to generate, based on a current flowing in the second resistive element, an analog output corresponding to an internal temperature of the photoelectric conversion device.

An adaptive sample and hold circuit for signal amplifier range selection is presented. The adaptive sample and hold circuit has an input for receiving an input signal and an output for providing a sample-and-hold-voltage. It also includes a sample-and-hold-capacitor to generate the sample-and-hold-voltage from the input signal, and a range detector. The range detector is adapted to identify a range of the input signal and to adjust a voltage at the sample-and-hold-capacitor based on the range of the input signal to maintain the sample-and-hold-voltage within a predetermined voltage span.

A method for testing an analog-to-digital converter unit, which is equipped to convert an analog input signal into a digital output signal with the aid of delta-sigma modulation. The method includes: generating an analog input signal; applying a predefined interference signal to the analog input signal and storing the resulting digital output signal as test result; determining that a fault is present if a transfer function of the analog-to-digital converter unit, which is ascertained from the test result and the input signal, has a deviation from a predefined target transfer function that is greater than a predefined reference value, a fault signal being output if a fault is determined.

A capacitance to digital converter, CDC, has a first and a second reference terminal for receiving first and second reference voltages, a reference block comprising one or more reference charge stores and being coupled to the first and second reference terminals via a first switching block, a scaling block for providing at third and fourth reference terminals downscaled voltages from the first and second reference voltages depending on a scaling factor, first and second measurement terminals for connecting a capacitive sensor element, the first measurement terminal being coupled to the third and fourth reference terminals via a second switching block, and a processing block coupled to the reference block and to the second measurement terminal and being configured to determine a digital output signal based on a charge distribution between the sensor element and the reference block and based on the scaling factor, the output signal representing a capacitance value of the sensor element.

An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.