A system may include a digital delta-sigma modulator configured to receive a digital audio input signal and quantize the digital audio input signal into a quantized signal, a filter configured to receive the quantized signal and perform filtering on the quantized signal to generate a filtered quantized signal, the filter having a variable group delay, and a current-mode digital-to-analog converter configured to receive the filtered quantized signal and convert the filtered quantized signal into an equivalent current-mode analog audio signal.

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

A signal density modulation (SDM) encoder includes a first subtractor, a sigma circuit and a multi-bit quantizer. The first subtractor is used for receiving an input signal. The sigma circuit is coupled to the first subtractor. The multi-bit quantizer, coupled to the first subtractor and the sigma circuit, is configured to generate an output signal. The sigma circuit or the multi-bit quantizer produces a first feedback signal to the first subtractor. The first subtractor performs a subtraction operation according to the first feedback signal and the input signal, and generates a delta signal. The sigma circuit performs an operation on the delta signal, such that the SDM encoder has a noise transfer function having a high pass filtering effect. The noise transfer function is a ratio of a quantization error brought by the multi-bit quantizer with respect to the input signal. The output signal has more than two levels.

An open-loop digital-to-analog converter (DAC) circuit may include a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to inputs of the plurality of DAC elements, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.

A delta-sigma (Σ-Δ) modulator and method for reducing nonlinear error and gain error. The Σ-Δmodulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

A communication apparatus (50) includes a path splitting unit configured to split an existing path into two paths, with one path being formed by appending 1 to the existing path and, the other path being formed by appending −1 to the existing path; a path metric sort unit (53) configured to sort the paths in the ascending order of their path metric values; and a path pruning unit (54) configured to choose L (L is an integer more than 1) paths which have lower path metric values; a select path unit (55) configured to select a path with lowest path metric among all available paths at the end of all the baseband samples and the selected path serving as the output bit sequence.

An open-loop digital-to-analog converter (DAC) circuit may include a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to inputs of the plurality of DAC elements, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.