Patent classifications
H03M5/16
ENCODING AND DECODING ARCHITECTURE FOR HIGH-SPEED DATA COMMUNICATION SYSTEM AND RELATED PHYSICAL LAYER CIRCUIT, TRANSMITTER AND RECEIVER AND COMMUNICATION SYSTEM THEREOF
A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.
Probability-based optimization of system on chip (SOC) power
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N.sub.P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.sub.P.
Probability-based optimization of system on chip (SOC) power
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N.sub.P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.sub.P.
EFFICIENT DATA ENCODING
Circuits, methods, and apparatus for efficiently implementing encoding and decoding between binary and multilevel data.
Apparatus and method for mapping binary to ternary and its reverse
Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.
Apparatus and method for mapping binary to ternary and its reverse
Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.
PROBABILITY-BASED OPTIMIZATION OF SOC POWER
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N.sub.P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.sub.P.
PROBABILITY-BASED OPTIMIZATION OF SOC POWER
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N.sub.P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.sub.P.
METHODS AND SYSTEMS FOR HIGH BANDWIDTH COMMUNICATIONS INTERFACE
A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.
Methods and systems for high bandwidth communications interface
Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.