Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N.sub.1 number of M.sub.1-ary signals, a second signal generator which receives the second input code and generates N.sub.2 number of M.sub.2-ary signals, and a first time division multiplexing module which temporally multiplexes the N.sub.1 number of M.sub.1-ary signals and the N.sub.2 number of M.sub.2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A.sub.2/A.sub.1) used for M.sub.1-ary and M.sub.2-ary signals to minimize a transmission error rate.

Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N.sub.1 number of M.sub.1-ary signals, a second signal generator which receives the second input code and generates N.sub.2 number of M.sub.2-ary signals, and a first time division multiplexing module which temporally multiplexes the N.sub.1 number of M.sub.1-ary signals and the N.sub.2 number of M.sub.2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A.sub.2/A.sub.1) used for M.sub.1-ary and M.sub.2-ary signals to minimize a transmission error rate.

Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N.sub.1 number of M.sub.1-ary signals, a second signal generator which receives the second input code and generates N.sub.2 number of M.sub.2-ary signals, and a first time division multiplexing module which temporally multiplexes the N.sub.1 number of M.sub.1-ary signals and the N.sub.2 number of M.sub.2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A.sub.2/A.sub.1) used for M.sub.1-ary and M.sub.2-ary signals to minimize a transmission error rate.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

A digital isolator can include: an encoding circuit configured to receive and encode an input digital signal, in order to generate an encoded signal, wherein a rising edge of the input digital signal is encoded as a first pulse sequence, and a falling edge of the input digital signal is encoded as a second pulse sequence; an isolation element coupled to the encoding circuit, and being configured to transmit the encoded signal in an electrically isolated manner; and a decoding circuit configured to receive the encoded signal through the isolation element, and to decode the encoded signal, in order to generate an output digital signal consistent with the input digital signal.

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

A method of sensor wire count reduction including receiving, from a sensor array comprising a first sensor, a second sensor, the third sensor, a first binary indication of sensor state for the first sensor a second binary indication of sensor state for the second sensor, and a third binary indication of sensor state for the third sensor. The method further includes setting a first voltage in response to the first binary indication of sensor state for the first sensor and the second binary indication of sensor state for the second sensor, determining a first indication comprising whether the fist voltage is within a first range, determining a second indication comprising whether the first voltage is within a second range, and determining a third indication comprising whether the first voltage is within a third range.

Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.