A method for determining a mapping between two code spaces is disclosed. The method may include receiving first and second plurality of data words. The least-significant-bits (LSBs) of a first data word of a first subset of the first plurality of data words may be compared to the LSBs of each data word of a second subset of the second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.

Operations include obtaining a binary source data set and determining a decimal value that represents the source data set. In addition, the operations include determining a Kinetic Data Primer (KDP) that represents the decimal value. The KDP may include a mathematical expression that represents the decimal value. Further, the operations may include storing the KDP as a compressed version of the source data set.

Operations include obtaining a binary source data set and determining a decimal value that represents the source data set. In addition, the operations include determining a Kinetic Data Primer (KDP) that represents the decimal value. The KDP may include a mathematical expression that represents the decimal value. Further, the operations may include storing the KDP as a compressed version of the source data set.

Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.

Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.

A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

Embodiments of the present disclosure relate to operations including obtaining a binary source data set and determining a decimal value that represents the source data set. In addition, the operations include determining a Kinetic Data Primer (KDP) that represents the decimal value. The KDP may include a mathematical expression that represents the decimal value. Further, the operations may include storing the KDP as a compressed version of the source data set.

Embodiments of the present disclosure relate to operations including obtaining a binary source data set and determining a decimal value that represents the source data set. In addition, the operations include determining a Kinetic Data Primer (KDP) that represents the decimal value. The KDP may include a mathematical expression that represents the decimal value. Further, the operations may include storing the KDP as a compressed version of the source data set.

Methods for encoding and decoding data. The encoding includes: receiving a datum representing a numerical value from a predefined maximum value range; selecting an encoding rule for the datum; encoding the numerical value of the datum based on the selected encoding rule by omitting all binary positions of the numerical value considered as a binary number that are of lower significance than a binary position used for the binary representation of a lower limit of a value range of the selected encoding rule, and all binary positions of the numerical value considered as a binary number that are of higher significance than a binary position used for the binary representation of an upper limit of the value range of the selected encoding rule; and extending the binary number of the encoded numerical value at a predefined position by predefined encoding information which uniquely identifies the encoding rule used.

A verify failbit count (VFC) circuit includes a counter circuit and a transcoder circuit. The counter circuit includes a counter. The counter is configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format. The transcoder circuit includes a transcoder coupled to the counter. The transcoder is configured to transcode the count result in unary format to a transcoded result in binary format.