A verify failbit count (VFC) circuit includes a counter circuit and a transcoder circuit. The counter circuit includes a counter. The counter is configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format. The transcoder circuit includes a transcoder coupled to the counter. The transcoder is configured to transcode the count result in unary format to a transcoded result in binary format.

Systems and methods for performing variable-bitwidth matrix multiplication are provided. For example, a processor device can include dot product hardware configured to perform a plurality of dot products at a first bitwidth to generate a plurality of first-bitwidth dot product outputs. The processor device can include programmable adder hardware. The programmable adder hardware can be configured to obtain data indicative of one or more target bitwidths. The programmable adder hardware can be configured to combine, based on the data indicative of the one or more target bitwidths, one or more subsets of the plurality of first-bitwidth dot product outputs according to the one or more target bitwidths.