A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.

A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2.sup.n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2.sup.n representation of the numerical value to be coded, wherein n is a natural number equal to or greater than 1.

A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2.sup.n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2.sup.n representation of the numerical value to be coded, wherein n is a natural number equal to or greater than 1.

A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.

An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.

A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Embodiments of methods and systems for BMC decoding are described. In an embodiment, a method for BMC decoding involves performing a unit interval estimation of a BMC encoded bit stream, locating a bit boundary of the BMC encoded bit stream based on the unit interval estimation and a known sequence in a preamble of the BMC encoded bit stream, and measuring a time duration across multiple bit transitions from the bit boundary and decoding the BMC encoded bit stream based on the time duration and the unit interval estimation.