Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Embodiments of the present application provide a method and a device for converting representations of values between RNS and CRNS. The present application can be used in any product to which RNS is applied. A compact RNS (called CRNS) is proposed by the present application, and a bijection between RNS representations and CRNS representations is created. The bijection maps between (n+1)-bit RNS representations and n-bit CRNS representations by using a logic function. The bijection maps only 2.sup.n values corresponding to an n-bit BNS value in a dynamic range [0, 2.sup.n1].

Embodiments of the present application provide a method and a device for converting representations of values between RNS and CRNS. The present application can be used in any product to which RNS is applied. A compact RNS (called CRNS) is proposed by the present application, and a bijection between RNS representations and CRNS representations is created. The bijection maps between (n+1)-bit RNS representations and n-bit CRNS representations by using a logic function. The bijection maps only 2.sup.n values corresponding to an n-bit BNS value in a dynamic range [0, 2.sup.n1].