The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2.sup.ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−s.sub.y)}≤k≤(ew−1) where s.sub.y=1 for a signed floating point number and s.sub.y=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2.sup.ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−s.sub.y)}≤k≤(ew−1) where s.sub.y=1 for a signed floating point number and s.sub.y=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

Systems and methods for mixed precision machine learning with fully homomorphic encryption are disclosed. A method may include receiving data in a mixed precision format from a program or an application executed by the client electronic device; converting the data from the mixed precision format to an integer format; encrypting the data in the integer format using a fully homomorphic data encryption scheme; communicating the encrypted data in the integer format to a host electronic device, wherein the host electronic device is configured to process the encrypted data in the integer format and provide an encrypted result in the integer format to the client electronic device; decrypting the encrypted result in the integer format using the fully homomorphic data encryption scheme; converting the decrypted result in the integer format to the mixed precision format; and outputting the result in the mixed precision format to the program or the application.

Systems and methods for mixed precision machine learning with fully homomorphic encryption are disclosed. A method may include receiving data in a mixed precision format from a program or an application executed by the client electronic device; converting the data from the mixed precision format to an integer format; encrypting the data in the integer format using a fully homomorphic data encryption scheme; communicating the encrypted data in the integer format to a host electronic device, wherein the host electronic device is configured to process the encrypted data in the integer format and provide an encrypted result in the integer format to the client electronic device; decrypting the encrypted result in the integer format using the fully homomorphic data encryption scheme; converting the decrypted result in the integer format to the mixed precision format; and outputting the result in the mixed precision format to the program or the application.

A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.

A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.

A system and method for generating and using fixed-point operations for neural networks includes converting floating-point weighting factors into fixed-point weighting factors using a scaling factor. The scaling factor is defined to minimize a cost function and the scaling factor is derived from a set of multiples of a predetermined base. The set of possible scaling function is defined to reduce the computational effort for evaluating the cost function for each of a number of possible scaling factors. The system and method may be implemented in one or more controllers that are programmed to execute the logic.

A system and method for generating and using fixed-point operations for neural networks includes converting floating-point weighting factors into fixed-point weighting factors using a scaling factor. The scaling factor is defined to minimize a cost function and the scaling factor is derived from a set of multiples of a predetermined base. The set of possible scaling function is defined to reduce the computational effort for evaluating the cost function for each of a number of possible scaling factors. The system and method may be implemented in one or more controllers that are programmed to execute the logic.