An aspect of the present invention is a communication system including: an encoding unit configured to transform an input symbol sequence into an output symbol sequence, the input symbol sequence being a sequence of first symbols, the output symbol sequence being a sequence of second symbols; and a decoding unit configured to transform the output symbol sequence into the input symbol sequence in accordance with a decoding-side transformation mapping for transforming the output symbol sequence into the input symbol sequence that is a transformation source for the output symbol sequence, wherein the encoding unit transforms the input symbol sequence into the output symbol sequence in accordance with encoding-side transformation destination candidate information, the input symbol sequence, and a transformation probability, the encoding-side transformation destination candidate information being information indicating candidates of a transformation destination for the input symbol sequence, the transformation probability being a probability of transformation into the transformation destination indicated by the encoding-side transformation destination candidate information, and a probability of appearance of the second symbol conforms to a predefined prescribed probability distribution.

Systems or methods for losslessly compressing data received from sensors, such as photon counters, are disclosed. An integer representation of a sensor reading is received from a sensor. The integer representation is combined with additional integer representations from each of a plurality of additional sensors into a single integer value. The single integer value is then stored as an element of an integer array that represents a predefined sample interval.

A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

A method for loop escape analysis includes receiving a set of executable computer instructions stored on a storage medium, and determining a number of inputs to a loop associated with a data structure, storage space that would be saved by compressing the data structure, and a size of new elements required to compress the data structure. Upon reaching an end of the loop, the method determines whether to compress the data structure based on a comparison between the size of the new elements and the saved storage space. In response to determining to compress the data structure, the method compresses the data structure.

A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

Tiers of compression algorithms may be determined using compression information collected regarding compression ratios achieved for data sets using compression algorithms. Each tier may meet specified criteria regarding expected compression ratios achieved for a specified portion or number of data sets. Compression algorithms of each tier may be implemented by a different hardware device that may include hardware accelerators for the algorithms of the tier. Different tiers, and thus different hardware devices, achieve different levels of compression. A recommendation may be provided using compression information collected, such as from one of the hosts, regarding which hardware device to use for compression. The recommendation may be to purchase a license to use or whether to purchase a particular hardware device for compression. Compression information may be collected by a host that issues tagged I/Os providing a hint regarding what compression algorithm to use for the particular I/O operation data.

An apparatus comprises a processing device configured to collect system state information from host devices, to split the collected system state information into logical chunks, and to determine, based at least in part on a plurality of factors, a compression level to be applied to each of the logical chunks. The plurality of factors comprise a first factor characterizing a time at which the collected system state information is needed at a destination device and at least a second factor characterizing resources available for at least one of performing compression of the collected system state information and transmitting the collected system state information over at least one network to the destination device. The processing device is further configured to apply the determined compression level to each of the logical chunks to generate compressed logical chunks, and to transmit the compressed logical chunks to the destination device.

A first storage system compresses data relating to read and write by a primary site and stores the data in a first physical volume. A second storage system compresses data relating to read and write by a secondary site and stores the data in a second physical volume. When performing replication for transferring the data stored in the first physical volume of the first storage system to the second storage system and storing the data in the second physical volume, the first storage system and the second storage system determine, based on a compression scheme executable by the first storage system and a compression scheme executable by the second storage system, a compression scheme to be applied to transfer target data and transfer the transfer target data compressed by the determined compression scheme.

Page filtering in a database using a compression dictionary. A page of a database table is compressed, creating a compression dictionary. The compression dictionary includes entries with a byte sequence from the page and a compression symbol associated with the byte sequence. A part of the compressed page, the compression dictionary, and a page symbol list with compression symbols from the dictionary present in the part of the page, are received. A query having a predicate with a predicate value is received. A predicate symbol list, including symbols in the dictionary whose byte sequences at least partially match the predicate value, is generated. Based on the predicate symbol list and the page symbol list, it is determined that at least one symbol from the predicate symbol list is also present in the part of the page. The query is performed by evaluating the predicate on the part of the page.

A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.