An encoding method includes obtaining to-be-encoded information and a mother code length N. The to-be-encoded information includes K information bits. The method also includes determining, based on K and N, a set I corresponding to subchannels of the information bits and a set F corresponding to subchannels of frozen bits. Information bits corresponding to subchannel sequence numbers in the set I are distributed in X outer component codes, a code length of each outer component code is B, and the X outer component codes includes a first-type outer component code and a second-type outer component code or the X outer component codes include a first-type outer component code, a second-type outer component code, and one third-type outer component code. Different types of component codes have different code rates. The method additionally includes performing polarization encoding based on the set I and the set F.

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This reduces encoding/decoding complexity.

In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method capable of ensuring good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 1224 or 1152 bits and the coding rate r of 144/1224 or 144/1152. The parity check matrix includes an A matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K=Nr of the LDPC code, a B matrix of a staircase structure of M1 rows and M1 columns, a Z matrix which is a zero matrix of M1 rows and NKM1 columns, a C matrix of NKM1 rows and K+M1 columns, and a D matrix which is an identity matrix of NKM1 rows and NKM1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of the elements of 1 of the A matrix and the C matrix for every 36 columns, and is a predetermined table. The present technology can be applied to, for example, data transmission using an LDPC code.

Embodiments of this application disclose a polar code encoding method, a polar code decoding method, and apparatuses thereof, to reduce encoding and decoding complexity. The method in embodiments of this application includes: generating an input vector, where the input vector includes T subblocks, a first information bit of a first subblock is obtained by replicating a second information bit of a second subblock, the first subblock and the second subblock are subblocks of the T subblocks, a sequence number of the first subblock is after a sequence number of the second subblock, and T is an integer greater than or equal to 2; and performing polar encoding on the input vector to obtain an encoded bit.

An encoding method, a decoding method, an electronic device and a storage medium are disclosed. The encoding method includes: acquiring stored data in a storage system, and acquiring nodes corresponding to the stored data to obtain a number of the nodes; dividing the acquired stored data into a sequence of information vectors, and generating an information matrix according to the number of the nodes and a number of the sequence of information vectors; and calculating an encoded block according to each information vector and the information matrix to obtain a sequence of encoded blocks.

A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding.

A construction method for a (n,n(n1),n1) permutation group code based on coset partition is provided. The presented (n,n(n1),n1) permutation group code has an error-correcting capability of d1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n1 and a code set size of n(n1), the invention provides a method of calculating n1 orbit leader permutation codewords by O.sub.n={o.sub.1}.sub.=1.sup.n1(mod n) and enumerating residual codewords of the code set by P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n1O.sub.n}={(r.sub.n).sup.n1O.sub.n)}. Besides, a generator of the code set thereof is provided. The (n,n(n1),n1) permutation group code of the invention is an algebraic-structured code, n1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers. Composition operations of the cyclic subgroup C.sub.n acting on all permutations o.sub. of the orbit leader permutation array O.sub.n are replaced by well-defined cyclic shift composite operation functions (l.sub.1).sup.n1 and (r.sub.n).sup.n1 so that the action of the cyclic group acting on permutations is realized by a group of cyclic shift registers.

A digital television transmitting system includes a frame encoder, a block processor, a group formatter, and a multiplexer. The frame encoder forms an enhanced data frame and encodes the data frame for error correction and for error detection. The block processor further encodes the encoded data frame at a rate of 1/2 or 1/4, and the group formatter divides the encoded data frame into a plurality of enhanced data blocks and maps the divided data blocks into a plurality of enhanced data groups, respectively. The multiplexer multiplexes the enhanced data groups with main data.