H03M13/033

MAGIC STATE FACTORY CONSTRUCTIONS FOR PRODUCING CCZ AND T STATES
20250181959 · 2025-06-05 ·

Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X.sup.1/2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z.sup.1/4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.

Method for polar code design with parity check bits

Error-correcting performance of polar codes is improved by assigning parity check bits to small, reliable indices. Zeros are assigned to message indices not among a most-reliable set of the message indices, information bits and parity check bits are assigned to the most-reliable set of the message indices, with the parity check bits generated on the information bits assigned to the smallest of the most-reliable set and then assigned to the smallest indices of the most-reliable set that follow the information bits on which the parity check pits are generated. During successive cancellation list decoding, the parity check bits allow error events to be promptly corrected during decoding.

Error correction code decoder using constacyclic code, and memory device and memory system including the same

An error correction code (ECC) decoder includes a syndrome generator and a burst error corrector. The syndrome generator generates global syndrome data and local syndrome data using input data and a parity check matrix based on a constacyclic code. The burst error corrector corrects a correctable error included in the input data using the global syndrome data and the local syndrome data. The input data includes a plurality of data bits arranged along a first direction and a second direction. The ECC decoder simultaneously corrects a single burst error and a multi-bit error. The single burst error occurs on two or more symbols arranged along the first direction in the input data, and each symbol includes two or more data bits. The multi-bit error randomly occurs on two or more data bits in the input data.

Non-linear encoding and decoding for reliable wireless communication

A method of encoding a set of information bits to produce a codeword that encodes the set of information bits for reliable communication is provided. The set of information bits is received. The set of information bits are provided to a plurality of permutation layers separated by neural network processing layers. Each permutation layer accepts an input vector and generates a reordered output vector that is a reordering of the input vector. Each neural network processing layer accepts a vector of input values and generates a vector of output values based on a non-linear function of the vector of input values. The reordered output vector of a final permutation layer of the plurality of permutation layers is provided as the codeword. In some embodiments, a corresponding method of decoding a codeword to retrieve a set of information bits is provided.

METHODS AND PROCEDURES FOR POLAR CODED MODULATION

Methods, apparatuses and systems are provided for constructing and modulating polar codes. Such procedures may involve identifying nonuniform channel conditions, selecting a modulation order, configuring a plurality of component codes and incremental ratios for Unequal Error Protection (UEP), identifying initial code construction parameters for each component code, calculating modified code construction parameters based on the incremental ratios for UEP, and encoding the component polar codes according to the modified construction parameters. Each component code may be comprised of a plurality of input bits. The initial and modified code construction parameters may include a number of unfrozen and frozen input bits, and identifying a number of unfrozen and frozen input bits may involve calculating and comparing reliability values for each bit. Calculating and comparing reliability values for each bit may involve applying a Polarization Weight (PW)-based method.

System and method for generation of error-correcting codes in communication systems
12519488 · 2026-01-06 ·

The present invention provide a system and method for generating a catalogue of graphs that acts as a source for error correcting codes. A D3 chord index notation is used to describe the graphs. A list of (3, g) Hamiltonian graphs for even girth g is created to satisfy the condition 6 g 16. Each of the lists is infinite and is used for creating LDPC codes of high quality. Furthermore, the embodiments herein generalizes the application scenario for usage of LDPC codes. The embodiments herein utilizes dynamically changing error-correction codes in wireless communication systems.