Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.

An encoding apparatus includes a processor a non-transitory computer-readable storage medium storing a program for encoding data into a codeword. The program includes instructions to encode the data x using a code that is a product of a matrix generated using the Kronecker product of the Q with itself and factors generated according to frozen bit indices of the code and a constraint matrix generated according to a precoding matrix.

The present disclosure provides a code generator for generating an {N, K} code for encoding and/or decoding data transmitted in a communication channel from an {N, K} code, wherein N and N are code lengths, K and K are code dimensions. The code generator is configured to shorten the {N, K} code to obtain an intermediate code, and to extend the intermediate code to obtain the {N, K} code. The present disclosure also provides a corresponding code construction method. Further, the present disclosure provides a device for encoding and/or decoding data transmitted in a communication channel, the device being configured to encode and/or decode the data based on an {N, K} code generated from the {N, K} code.

A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having A length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If A is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

The present disclosure provides an encoding method and apparatus, and relates to the field of communications technologies, to reduce an encoding latency and complexity, and the amount of computation of real-time construction. The encoding method includes: obtaining information bits; determining a puncturing pattern, where the puncturing pattern includes an element in a puncturing set and an element in a shortening set, and the puncturing set and the shortening set have no intersection set; and performing, by using the determined puncturing pattern, rate matching on data obtained after the information bits are encoded.

A polar-code based encoder is used to perform a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel. The Divide and Conquer structure consists of a multiplexer having useful data bits and a set of frozen bits as inputs followed by a polarization block of size N=2.sup.L, wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size. A dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure. The configuration of the dynamically configurable interleavers is dynamically modified according to changes detected in the Binary Discrete-input Memory-less Channel.

Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

A method for the redundant transmission of data by means of light-based communication may include a data stream to be transmitted that is converted into symbols. This data stream is converted from bipolar symbols into multiple partial data streams having e.g. unipolar-positive symbols. The partial data streams are converted into multiple semi-redundant signals that are then transmitted to the receiver via multiple light-based channels. In the receiver, the received signals are converted back again analogously to when they were sent, in order to obtain the original data stream again.

A construction method for a (n,n(n1),n1) permutation group code based on coset partition is provided. The presented (n,n(n1),n1) permutation group code has an error-correcting capability of d1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n1 and a code set size of n(n1), the invention provides a method of calculating n1 orbit leader permutation codewords by O.sub.n={o.sub.1}.sub.=1.sup.n-1(mod n) and enumerating residual codewords of the code set by P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n-1O.sub.n}={(r.sub.n).sup.n-1O.sub.n}. Besides, a generator of the code set thereof is provided. The (n,n(n1),n1) permutation group code of the invention is an algebraic-structured code, n1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers. Composition operations of the cyclic subgroup C.sub.n acting on all permutations o.sub. of the orbit leader permutation array O.sub.n are replaced by well-defined cyclic shift composite operation functions (l.sub.1).sup.n-1 and (r.sub.n).sup.n-1 so that the action of the cyclic group acting on permutations is realized by a group of cyclic shift registers.