An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.

The present invention discloses a decoding path selection device for decoding codewords generated by convolutional codes or turbo codes encoders in error correction codes, the decoding path selection device comprising: a branch metrics calculation unit for receiving incoming signals and calculating branch metrics values; a programmable generalized trellis router for generating a decoding path control signal according to the turbo code or convolutional code specification employed by one of communications standards; a multiplexer for receiving the branch metrics values from the branch metrics calculation unit and the decoding path control signal from the programmable generalized trellis router and selecting a corresponding branch metrics value; a recursive calculation unit, connected after the multiplexer and for receiving the corresponding branch metrics value from the multiplexer; and an a-posteriori probability calculation unit, connected after the recursive calculation unit and for calculating a final decoding result.

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

A memory system includes a memory device including a plurality of memory blocks and a controller suitable for selecting first memory blocks, the number of valid pages of which is equal to or less than a first threshold value, among the plurality of memory blocks, and performing a garbage collection operation on the first memory blocks based on error bit information of the first memory blocks.

The present invention relates to a digital broadcasting system for transmitting/receiving a digital broadcasting signal and a method of processing data. In one aspect of the present invention provides a method of processing data, the method including receiving a broadcasting signal in which mobile service data and main service data are multiplexed, demodulating the received broadcasting signal, obtaining an identifier indicating that data frame of the broadcasting signal includes service guide information, decoding and storing the service guide information from the data frame; and outputting a service included in the mobile service data according to the decoded service guide information.

In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and

in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

According to various embodiments, there may be provided a method of encoding data, the method including providing a set of replica nodes, wherein each replica node of the set of replica nodes stores replica data identical to original data stored in a corresponding original node of a set of original nodes; receiving original data at each replica node of the set of replica nodes, wherein the received original data is transmitted from the corresponding original node of a different replica node; generating a first result at each replica node, based on the replica data stored therein and the received original data; and generating a second result at each replica node, based on the replica data stored therein and the first result from a different replica node; and replacing the replica data in each replica node with the second result from the respective replica node.

Devices, systems and methods for convolutional precoding and decoding of polar codes are disclosed. An example method for error correction in a data processing system includes receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis, and performing, based on the trellis, a list-decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages.

A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.