Patent classifications
H03M13/251
Technologies for applying a redundancy encoding scheme to segmented network packets
Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
CODING AND MODULATION APPARATUS USING NON-UNIFORM CONSTELLATION
A coding and modulation apparatus and method are presented. The apparatus comprises an encoder that encodes input data into cell words, and a modulator that modulates said cell words into constellation values of a non-uniform constellation. The modulator is configured to use, based on the total number M of constellation points of the constellation and the signal-to-noise ratio SNR in dB, a non-uniform constellation from a group of constellations comprising one or more of predetermined constellations defined by the constellation position vector w.sub.0 . . . b−1, wherein b=M/4.
Methods and apparatus for encoding and decoding of data using concatenated polarization adjusted convolutional codes
An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}.sub.i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}.sub.1, {circumflex over (b)}.sub.2, . . . , {circumflex over (b)}.sub.i−1). The decoder carries out an outer decoding operation to generate from {tilde over (b)}.sub.i an outer decoder decision â.sub.i, and carries out a reencoding operation to generate a decision feedback {circumflex over (b)}.sub.i from â.sub.i, where the number of layers is an integer greater than one, with a concatenated decoder output block {circumflex over (d)} being generated from outer decoder decisions.
Error rate measuring apparatus and uncorrectable codeword search method
An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting unit for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search unit for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control unit for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.
Controller, semiconductor memory system and operating method thereof
An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.
ENCODER CIRCUIT, DECODER CIRCUIT, ENCODING METHOD, AND DECODING METHOD FOR MULTILEVEL CODING
Encoder circuit encodes information bits using 2.sup.2N signal points. The encoder circuit includes: symbol mapper that allocates each symbol of frame including information bits, first code and second code to a corresponding signal point among 2.sup.2N signal points according to mapping pattern; converter that converts information bits in other bit strings among N bit strings forming the frame excluding MSB string by using probabilistic shaping; first encoder that generates the first code from information bits in MSB string and the information bits converted by the converter; and second encoder that generates the second code from the information bits in MSB string and the first code. In the mapping pattern, values of bits corresponding to the other bit strings are arranged symmetrically in the constellation, and each pair of adjacent signal points on the constellation are different from each other in terms of value of bit corresponding to MSB string.
Method and apparatus for data transmission mitigating interwire crosstalk
Data transmission mitigating interwire crosstalk including: dividing a data block to be transmitted from a transmitter to a receiver across a set of signal wires into sub-blocks; encoding each of the sub-blocks into a plurality of codewords; selecting, for each sub-block by a cost function, one of the codewords that is less likely to introduce interwire crosstalk; transmitting the selected codewords; and updating the cost function at the transmitter with feedback from the receiver.
Controller, semiconductor memory system and operating method thereof
An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.
POLAR CODES AND MODULATION MAPPINGS
Methods, systems, and devices for wireless communication are described. A transmitter, such as a user equipment and/or a base station, may perform polar coding to encode bits. The polar coding may be associated with a plurality of component channels associated with a polar code length. The transmitter may interleave the encoded bits. The transmitter may map the interleaved encoded bits to a modulation symbol. The interleaving and mapping of each encoded bit may be based on an asymmetry of a polar code construction. The transmitter may transmit the interleaved encoded bits based on the mapping.
Methods and systems for data transmission
The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.