A wireless communication method for transmitting wireless signals from a transmitter includes dividing bits of the transport block into a number of code blocks, wherein each code block corresponds to a bit-level of a multi-level modulation scheme used for transmission, and wherein a size of each code block is inversely proportional to a corresponding coding rate used for coding the code block.

Provided are a processing method, device, and system for an overlapped multiplexing system. The method includes: receiving encoded information output by a transmit end, where the encoded information is information obtained by performing error-correcting code encoding and overlapped multiplexing encoding on input information; decoding the encoded information according to an overlapped multiplexing decoding algorithm, to obtain a first decoding result; performing error-correcting processing on the first decoding result according to an error-correcting code decoding algorithm, to obtain a second decoding result; and outputting the second decoding result.

A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

A data retransmission method for a polar code, and a device therefor are disclosed. The data retransmission method of the disclosure can comprise the steps of: generating a first data block by allocating a plurality of data bits to input bits, with high priorities, among input bits of a polar code encoding module on the basis of a target encoding rate; transmitting the generated first data block; generating a second data block by allocating first data bits among the plurality of data bits to input bits, with low priorities, among the input bits of the polar code encoding module, on the basis of the target encoding rate and shortening bits; and transmitting the generated second data block as a retransmission of the first data block.

Modern mobile communication systems transfer data by error protection measures including the use of a forward error correction code for the channel coding and a HARQ (hybrid automatic repeat request) system for the repeated transfer of incorrect transport blocks in response to the error protection mechanisms failing. When a turbo code is used as an error protection code, two decoders work on the decoding of the turbo code. Disclosed is an expanded HARQ system wherein the receiving side determines which of the decoders was more greatly challenged in the decoding of the turbo code and reports this to the transmitting side. Instead of uniformly providing more redundancy data to both decoders, more redundancy data are targetedly provided to the more greatly challenged decoder in the expanded HARQ process than in the case of the repetition operation according to the typical HARQ process reducing the latency of the data transfer.

The memory system includes a memory device including a volatile storage area and a non-volatile storage area; and a controller including first and second interfaces for transferring data between the memory system and a host, and suitable for transferring data between the volatile storage area and the host through the first interface and transferring data between the non-volatile storage area and the host through the second interface, wherein the controller is further suitable for determining whether or not an error occurs in data read from the volatile storage area in a normal operation mode, and dumping a whole of the volatile storage area into a predetermined first location of the non-volatile storage area when an error is determined to occur in the data read from the volatile storage area.

Devices and methods for enhancing forward error correction techniques for communications using chirp spread spectrum are disclosed. Systems, devices, and methods for error correction coding and decoding are described. On the coding side, K bits of data are sequentially loaded into an M bit by N bit (MN) matrix in a first direction as Q sequences of D bits, each D bit row of data in the MN matrix is coded with an error correction code to generate an M bit row of coded data, each Q bit column in the MN matrix is coded with the error correction code to generate N bits of coded data, N sequences of M bits are sequentially unloaded from the MN matrix in a second direction, and a chirp signal is generated having a plurality of chirps.

A syndrome-based decoding method and apparatus for a block turbo code are disclosed. An embodiment of the present invention provides a syndrome-based decoding method for a block turbo code that includes an extended Hamming code as a component code, where the decoding method includes: (a) generating an input information value for a next half iteration by using channel passage information and the extrinsic information and reliability factor of a previous half iteration; (b) generating a hard decision word by way of a hard decision of the input information value; (c) calculating an n number of 1-bit syndromes, which corresponds to the number of columns or rows of the block turbo code, by using the hard decision word; and (d) determining whether or not to proceed with the next half iteration by using the calculated n number of 1-bit syndromes.