H03M13/2735

DE-INTERLEAVING CIRCUIT AND DE-INTERLEAVING METHOD
20180077447 · 2018-03-15 ·

A de-interleaving circuit that performs a time de-interleaving process on an interleaved block of an interleave signal includes: an input buffer, buffering multiple information units included in a time interleaved block; a writing address generator, generating multiple writing addresses according to a predetermined rule to write the information units buffered in the input buffer to a memory; a reading address generator, generating multiple reading addresses according to the predetermined rule to read the information units from the memory; and an output buffer, buffering the information units read from the memory. The information units are stored in multiple tiles of the memory. The tiles correspond to multiple regions of the time interleaved block, the multiple regions include a first region and a second region, and the dimensions of each tile in the first region are different from the dimensions of each tile in the second region.

Method for generating burst error correction code, device for generating burst error correction code, and recording medium storing instructions to perform method for generating burst error correction code

There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.

POWER-IMBALANCED MULTI-LEVEL DECODING METHOD AND SYSTEM FOR SPARSE CODE MULTIPLE ACCESS
20260074716 · 2026-03-12 ·

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.