A receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

A Polar code rate matching method and a rate matching apparatus are disclosed. The method includes: dividing a system Polar code output by a Polar code encoder into system bits and parity bits; interleaving the system bits to obtain a first group of interleaved bits, and interleaving the parity bits to obtain a second group of interleaved bits; and determining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits. System bits and parity bits are separately interleaved, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance, and ensuring reliability of data transmission.

The present invention relates to a method for performing channel encoding by a transmitting end in a wireless communication system. Particularly, the method comprises the steps of: transmitting, to a receiving end, a configuration indicating a plurality of channel coding configurations; performing channel encoding using a first channel coding configuration among the plurality of channel coding configurations; and performing reconfiguration from the first channel coding configuration to a second channel coding configuration according to a change in system requirements, wherein the plurality of channel coding configurations comprise channel coding configurations, each comprising at least one channel code concatenated differently according to the system requirements.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A Polar code rate matching method and a rate matching apparatus are disclosed. The method includes: dividing a system Polar code output by a Polar code encoder into system bits and parity bits; interleaving the system bits to obtain a first group of interleaved bits, and interleaving the parity bits to obtain a second group of interleaved bits; and determining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits. System bits and parity bits are separately interleaved, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance, and ensuring reliability of data transmission.

A method for resource allocation is applied to user equipment or a network side device. The method includes: determining a resource allocation scheme, the resource allocation scheme being performing resource allocation based on a cubic permutation polynomial (CPP) interleaver; performing resource allocation according to the resource allocation scheme; and sending configuration information, wherein the configuration information is used to determine an allocated resource.