A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Embodiments of the present invention provide a polar code rate matching method and a polar code rate matching apparatus. The method includes: performing matrix-based BRO interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; and determining, based on the interleaved bits, a rate-matched output sequence. According to the embodiments of the present invention, matrix-based BRO interleaving is performed on a non-systematic polar code, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission.

A polar code rate matching method and apparatus are provided. The method includes: performing bit reversal order interleaving on a polar code output by a polar code encoder, to obtain interleaved bits; and determining, based the interleaved bits, a rate-matched output sequence. By performing bit reversal order interleaving on a polar code, a rate-matched output sequence is obtained, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission.

A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.