H03M13/2792

Parallel bit interleaver
11362680 · 2022-06-14 · ·

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Method and apparatus for generating redundant bits for error detection
11362679 · 2022-06-14 · ·

A redundant bit generating device that generates redundant bits for error detection, that are added to a block of information bits, includes: a redundant bit calculation function that generates a predetermined number of redundant bits from the information bits according to a CRC polynomial; and a bit interleaving function that dispersedly arranges the predetermined number of redundant bits within the information bits using a permutation pattern determined based on the CRC polynomial.

Data receiving method and device, and data sending method and device

An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.

Systems and methods for interleaved hamming encoding and decoding

A communication device includes a first alignment circuit configured to receive, from a host device, a first encoded data stream including a plurality of symbols encoded with a first type of error correction code. The first alignment circuit is configured to output an aligned first encoded data stream that is aligned to boundaries between the plurality of symbols encoded with the first type of error correction code. An interleaver is configured to interleave the plurality of symbols of the aligned first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. An encoder is configured to generate, for each of the symbol sections, a parity block corresponding to the symbols in the symbol section and to output a second encoded data stream including the aligned first encoded data stream and the parity block.

Transmitting apparatus and bit interleaving method thereof

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALING

Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 4096-symbol mapping, and bit interleaving method using same

A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 4096-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 3/15.

Method and apparatus for processing rate matching of polar codes
11342945 · 2022-05-24 · ·

Provided is a rate matching method and device for a Polar code. The method includes: concatenating K information bits and (N−K) frozen bits to generate a bit sequence of N bits, and encoding the bit sequence of N bits by means of a Polar code encoder with a generator matrix of size N×N to generate an initial bit sequence {S.sub.0, S.sub.1, . . . , S.sub.N−1} of bits, where K and N are both positive integers and K is less than or equal to N; dividing a circular buffer into q parts, selecting bits from the initial bit sequence {S.sub.0, S.sub.1, . . . , S.sub.N−1} in a non-repeated manner, and writing the bits into the q parts of the circular buffer according to a predefined rule, where q=1, 2, 3 or 4; and sequentially selecting a bit sequence of a specified length from a predefined starting position in a bit sequence in the circular buffer and taking the bit sequence of the specified length as a bit sequence to be transmitted.

Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals

The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.