Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

Disclosed in the present specification is a method for performing channel encoding. The method can comprise the steps of: interleaving information bits; and encoding the interleaved information bits by using a polar code. The information bits can be interleaved according to an interleaving pattern.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

The application provides a channel encoding method, an encoding apparatus, and a system. A bit sequence X.sub.1.sup.N is output by using X.sub.1.sup.N=D.sub.1.sup.NF.sub.N, where D.sub.1.sup.N is a bit sequence obtained after an input bit sequence u.sub.1.sup.N is encoded based on locations of K to-be-encoded information bits in an encoding diagram that has a mother code length of N, u.sub.1.sup.N is a bit sequence obtained based on the K to-be-encoded information bits, and F.sub.N is a Kronecker product of log.sub.2 N matrices F.sub.2. A design considers that the locations of the K to-be-encoded information bits in the encoding diagram that has a mother code length of N include a row location index set H of the information bits in the encoding diagram and a layer location index set M of the information bits in the encoding diagram, where 0≤H≤N, and 0<M≤log.sub.m N−1.

Methods and apparatus for selection of memory devices in a distributed storage network. In an embodiment, a computing device receives a data object for storage and forwards the data object to a buffer for temporary storage, the buffer comprised of a first memory devices of a first memory type. A system level storage efficiency is determined for the data object based, at least in part, on a data attribute associated with the data object. Second memory devices, of a second memory type, are selected based on the system level storage efficiency preference, and compatible dispersed storage error encoding parameters for the data object are determined. The data object is encoded using the encoding parameters to generate a plurality of encoded data slices, which are provided to the second plurality of memory devices for storage. Further, system addressing information is generated based on an identifier associated with the data object.

For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Apparatus for tiered storage of data in a storage network. In an example of operation, a computing device receives a data object for storage and forwards the data object for storage in a first plurality of memory devices of a first memory type. The computing device determines a system level storage efficiency for the data object based, at least in part, on a data attribute associated with the data object. The computing device further selects, based at least in part on the system level storage efficiency preference, a second plurality of memory devices comprised of a second memory type. The computing device determines error encoding parameters based on the second plurality of memory devices, retrieves the data object from the first plurality of memory devices, and encodes the data object with the error encoding parameters to generate a plurality of encoded data slices for storage in the second plurality of memory devices.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.